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| WM8170 3.3V Integrated Signal Processor for Area Array CCDs Product Preview Rev 1.0 March 2000 DESCRIPTION The WM8170 is a 10-bit analogue front end/digitiser IC, which processes and digitises the analogue output signals from area array CCD sensors at pixel sample rates of up to 21MSPS. The device contains input blanking, correlated double sampling (CDS), programmable gain amplifier, black level clamp, on-board voltage reference and a 10-bit, 21MSPS ADC. Two auxiliary 8 bit DACs are provided which may be used for bias voltage control or camera functions such as auto-focus. Fine black level adjustment is performed digitally after the ADC. This digital adjustment will follow DC shifts in the video input without introducing digital correction noise into the image. The WM8170 is designed to interface to a wide range of area array CCDs and can operate at lower power for slower sample rates by setting the reference bias current via an external resistor connected to the ISET pin. All signal timing within the device is derived from the CCD clock signals. The WM8170 is controlled via a configurable serial interface, which is compatible with all of Wolfson' s imaging devices. The user is able to control the device functions and monitor on-chip register settings via the easy-to-use digital management interface. FEATURES * * * * * * * * * * * * * * * 10-bit, 21MSPS ADC No missing codes guaranteed Correlated double sampling Programmable gain amplifier Black level clamp Input blanking Two auxiliary 8-bit DACs Power save mode Serial or parallel control bus Adjustable sample rate User selectable sampling on rising or falling edge of clocks Single 3.3V power supply (3V minimum) 48-pin TQFP package Standby mode ICC<10A Power consumption typically 190mW at 12MHz, 270mW at 21MHz APPLICATIONS * * * * * Digital still cameras Digital camcorders PC cameras Progressive scan CCDs NTSC, PAL interline CCDs BLOCK DIAGRAM VRB VMID VRT (15) (16) (14) BLCENB (27) SHP SHD (22) (21) CVDD (42) AVDD[1-3] DVDD[1-4] DCLK (10,11,20) (3,23,33,39) (38) VCLP (12) REFERENCE CLPENB (24) CLPSWB (25) PIN (19) DIN (18) PBLK/HD (26) Dual Mode Pin ANALOGUE BLACK LEVEL CLAMP TIMING GENERATOR DIGITAL COMPARATOR DIGITAL BLACK LEVEL CLAMP AND FILTER (8) PTDO (31) OEB CLAMP CDS S/H PGA 10-BIT ADC HI-Z DATA I/O (1,4-7,44-48) VOUT1 (40) 8-BIT ADC 8-BIT ADC WM8170 CONFIGURABLE SERIAL/PARALLEL INTERFACE (29) PNS (36) SEN/STB (37) SCK/RNW (35) SDI/DNA (32) NRESET (34) SDO (30) PDB/VD Dual Mode Pin VOUT2 (41) BIAS CIRCUIT (43) CGND (9,17) AGND[1-2] (13) ISET (2,28) DGND[1-2] WOLFSON MICROELECTRONICS LTD. Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk Product Preview data sheets contain specifications for products in the formative phase of development. These products may be changed or discontinued without notice. (c) 2000 Wolfson Microelectronics Ltd. WM8170 PIN CONFIGURATION SCL/RNW DVDD1 DCLK VOUT2 VOUT1 Product Preview Rev 1.0 ORDERING INFORMATION DEVICE TEMP. RANGE 0 to 70 C o PACKAGE 48-pin TQFP CGND D5 DGND2 DVDD4 D6 D7 D8 D9 PTDO AGND1 AVDD1 AVDD3 VCLP 1 2 3 4 5 6 7 8 9 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 CVDD XWM8170CFT/V D4 D3 D2 D1 D0 SEN/STB SDI/DNA SDO DVDD3 NRESET OEB PDB/HD PNS DGND1 BLCENB PBLK/HD CLPSWB WM8170 10 11 12 25 13 14 15 16 17 18 19 20 21 22 23 24 VRB VMID PIN AVDD2 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per JEDEC specifications A112-A and A113-A this product requires specific storage conditions prior to surface mount assembly and as such will be supplied in vacuum sealed moisture barrier bags. CONDITION Analogue supply voltages (AVDD1 to AVDD3) Digital supply voltages (DVDD1 to DVDD4) Clock supply voltage, CVDD Digital inputs BLCENB, CLPENB, CLPSWB, PBLK, SHD, SHP pins Digital inputs PDB, NRESET, SCK/RNW, SEN/STB, PNS, SDI/DNA, OEB, DCLK, SDO pins Digital outputs, D0 to D9, PTDO Analogue inputs and analogue outputs Maximum difference between AGND, DGND and CGND Maximum difference between DVDD1, AVDD and CVDD Operating temperature range, TA Storage temperature Lead temperature (soldering, 10 seconds) Note 1: CLPENB AGND2 DIN SHP DVDD2 ISET VRT SHD MIN AGND -0.3V DGND -0.3V CGND -0.3V DGND -0.3V DGND -0.3V DGND -0.3V AGND -0.3V - 0.1V - 0.1V 0C -65 C o o MAX AGND +7V DGND +7V CGND +7V DVDD2 +0.3V DVDD3 +0.3V DVDD4 +0.3V AVDD +0.3V +0.1V +0.1V +70 C +150 C +260 C o o o Note 2: AGND denotes the voltage on any analogue ground pin. DGND denotes the voltage on any digital ground pin. CGND denotes the voltage on the clock ground pin. For this device all GND pins should be star connected as close as possible to the device. AVDD denotes the voltage on any AVDD pin. For this device all AVDD supplies should be connected together. PP Rev 1.0 March 2000 WOLFSON MICROELECTRONICS LTD 2 WM8170 Product Preview Rev 1.0 RECOMMENDED OPERATING CONDITIONS SHD/SHP = 21MHz RISET=15k PARAMETER Supply voltage Analogue supply current - active Digital supply current - active (Note 1) Clock supply current - active Supply current - standby (Total) IAACT IDACT ICACT ISDBY SHD/SHP = 0MHz SYMBOL TEST CONDITIONS MIN 2.97 68 8 6 10 10 TYP MAX 3.63 80 UNIT V mA mA mA A SHD/SHP = 12MHz RISET=22k PARAMETER Supply voltage Analogue supply current - active Digital supply current - active (Note 1) Clock supply current - active Supply current - standby (Total) Note 1: IAACT IDACT ICACT ISDBY SHD/SHP = 0MHz SYMBOL TEST CONDITIONS MIN 2.97 50 4 4 10 TYP MAX 3.63 UNIT V mA mA mA A Digital supply current - active includes DVDD4 current, which is dependent on the D[9:0] capacitive load. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 3 WM8170 PIN DESCRIPTION PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 D5 DGND2 DVDD4 D6 D7 D8 D9 PTDO AGND1 AVDD1 AVDD3 VCLP ISET VRT VRB VMID AGND2 DIN PIN AVDD2 SHD SHP DVDD2 CLPENB CLPSWB PBLK/HD BLCENB DGND1 PNS PDB/VD OEB NRESET DVDD3 SDO SDI/DNA SEN/STB SCK/RNW DCLK DVDD1 VOUT1 VOUT2 CVDD CGND D0 D1 D2 D3 D4 NAME Digital IO Supply Supply Digital IO Digital IO Digital IO Digital IO Digital output Supply Supply Supply Analogue output Analogue output Analogue output Analogue output Analogue output Supply Analogue input Analogue input Supply Digital input Digital input Supply Digital input Digital input Digital input Digital input Supply Digital input Digital input Digital input Digital input Supply Digital tri-stateable output Digital input Digital input Digital input Digital input Supply Analogue output Analogue output Supply Supply Digital output Digital output Digital IO Digital IO Digital IO TYPE DESCRIPTION Data output 5/parallel data IO3 Digital ground for D0 to D9, PTDO pins Digital supply for D0 to D9, PTDO pins Data output 6/parallel data IO4 Data output 7/parallel data IO5 Data output 8/parallel data IO6 Data output 9 (MSB)/parallel data IO7 Programmable threshold detect output Analogue ground and device substrate Analogue supply for ADC Analogue supply for references, bias voltage Reset level clamping voltage output External resistor for bias current control Upper ADC reference voltage output Lower ADC reference voltage output Midrail reference voltage output Analogue ground and device substrate Video data input Video preset input Product Preview Rev 1.0 Analogue supply for S/H, PGA, analogue DC correction loop and auxiliary DACs Sample and Hold data control Sample and Hold preset control Digital supply BLCENB, CLPENB, CLPSWB, PBLK, SHD, SHP pins Reset level clamp enable input, active low Reset level clamp enable switch, active low Input blocking control, active low/Horizontal drive timing signal input Black level clamp control, active low Digital ground for DVDD1, DVDD2, DVDD3 supplies Parallel not serial control External power down, active low/Vertical drive timing signal input Output enable bar, active low Master chip reset, active low Digital supply for PDB, NRESET, SCK/RNW, SEN/STB, PNS, SDI/DNA, OEB, DCLK, SDO pins Serial data output, tri-stateable Serial data in/parallel data not address (management interface) Serial enable/parallel strobe (management interface) Serial clock/parallel read not write (management interface) Output data retiming clock input Digital supply for internal logic Auxiliary DAC1 output Auxiliary DAC2 output Positive supply for internal clock generation circuitry Ground for internal clock generation circuitry Data output 0 (LSB), tri-stateable Data output 1, tri-stateable Data output 2/parallel data IO0 Data output 3/parallel data IO1 Data output 4/parallel data IO2 PP Rev 1.0 March 2000 WOLFSON MICROELECTRONICS LTD 4 WM8170 Product Preview Rev 1.0 ELECTRICAL CHARACTERISTICS Test Characteristics CVDD = AVDD = DVDD = 3.3V, AGND = DGND = CGND = 0V, RISET=15k , TA = 0oC to +70oC, unless otherwise stated. PARAMETER Digital Inputs High level input voltage Low level input voltage High level input current Low level input current Input capacitance Digital Outputs High level output voltage Low level output voltage High impedance O/P current Analogue Inputs Input common mode range Resolution Maximum differential nonlinearity Maximum integral nonlinearity Maximum sampling rate CDS S/H Maximum input voltage for full scale ADC output VINMAX PGA = 00hex TIMES2 0 1 0 1 PGA = FFhex V375 TIMES2 0 0 0 1 1 0 1 1 V375 0 0 1 1 VINMIN TIMES2=0, V375=1 TIMES2=1, V375=1 TIMES2=0, V375=1 TIMES2=1, V375=1 5 27 33 8 PDNL PINL DNL INL SMAX PGA at minimum gain PGA at minimum gain 21.5 +/-2 VCMR 0.3 10 +/-1 AVDD-0.3 V Bits LSB LSB MSPS 10-bit ADC Performance Including CDS and PGA Functions NO MISSING CODES GUARANTEED VOH VOL IOZ IOH = 1mA IOL = 1mA DVDD-0.6 0.6 1 V V A VIH VIL IIH IIL CIN 5 0.8*DVDD 0.2*DVDD 1 1 V V A A pF SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 1 0.5 1.5 0.75 V V V V Minimum input voltage for full scale ADC output 40 20 60 30 0 6 28 34 0.11 7 29 35 mV mV mV mV dB dB dB dB dB Bits LSB LSB PGA Minimum gain Minimum gain Maximum gain Maximum gain LSB step size Resolution PGA maximum differential non-linearity PGA maximum integral non-linearity GNTMIN GTMIN GNTMAX GTMAX GLSB WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 5 WM8170 Test Characteristics Product Preview Rev 1.0 CVDD = AVDD = DVDD = 3.3V, AGND = DGND = CGND = 0V, RISET=15k , TA = 0oC to +70oC, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS Reset Level Clamp Switch/AC Coupling Resistance AC coupling resistance, ON AC coupling resistance, OFF Reset level clamp switch resistance Black Level Clamp DC offset correction range References VMID voltage VRT - VRB, Note 1 VRT - VRB, Note 1 VCLP voltage referenced to VMID VMID VREFL VREFH VCOOO VCO1O VC1OO VCOO1 VCO11 VC1O1 VISET VITEMP 8 INL DNL DFSO DFSOH DSR DTS DLR AUX1X1, AUX2X1 = 0 AUX1X1, AUX2X1 = 1 AVDD AVDD/2 +1 +0.75 VCLP[1.0] 00 01 10 00 01 10 V375=0 V375=1 V375 0 0 0 1 1 1 1.203 1.575 1.65 0.5 0.75 -0.25 0 +0.25 -0.375 0 +0.375 1.234 1.725 V V V V V V V V V V mV/oC Bits LSB LSB V V V/ sec sec mV/mA VBLCR V375=1 80 mV RCON RCOFF RON ACINP=1 ACINP=0 ACINP=0, CLPENB=0 CLPSWB=0 MIN 30 20 115 150 185 TYP 50 MAX 70 UNIT k M Voltage on ISET pin VISET temperature coefficient Auxiliary DACs Resolution Maximum integral nonlinearity Maximum differential nonlinearity Full scale output, TIMES 2 Full scale output, TIMES 1 Output slew rate Output settling time Load regulation 1.265 Note 1: ADC input voltage is twice VRT- VRB voltage. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 6 WM8170 Product Preview Rev 1.0 DETAILED TIMING DIAGRAMS INPUT VIDEO SAMPLING tSHD SHD tSHP SHP tPD DIN, PIN, INPUT VIDEO tRSU tRH tVSU tVH tPTOD tDTOP tDP Figure 1 Input Video Sampling Diagram Test Characteristics CVDD = AVDD = DVDD = 3.3V, AGND = DGND = CGND = 0V, RISET=15k , TA = 0oC to +70oC, unless otherwise stated. PARAMETER Input video (DIN) set-up time with reference to SHD trailing edge Input video (DIN) hold time with reference to SHD trailing edge Reset video (PIN) set-up time with reference to SHP trailing edge Reset video (PIN) hold time with reference to SHP trailing edge SHD active low time SHP active low time SHP high to SHD low time SHD high to SHP low time SHD trailing edge to SHP trailing edge SHP trailing edge to SHD trailing edge SYMBOL tVSU tVH tRSU TEST CONDITIONS MIN 5 5 5 TYP MAX UNIT ns ns ns tRH tSHD tSHP tPTOD tDTOP tDP tPD 5 7.5 7.5 10 10 21.4 21.4 ns ns ns ns ns ns ns WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 7 WM8170 OUTPUT DATA SHD tCKL DCLK tSHDC OEB tSHDO D[9:0], RETIME=0 tDCDO D[9:0], RETIME=1 tSHPT PTDO, RETIME=0 PTDO, RETIME=1 tDCPT tPEZ tCKH tPER Product Preview Rev 1.0 tPZE Figure 2 Output Data Timing Diagram Test Characteristics CVDD = AVDD = DVDD = 3.3V, AGND = DGND = CGND = 0V, RISET=15k , TA = 0oC to +70oC, unless otherwise stated. PARAMETER DCLK period DCLK high DCLK low Output propagation delay, RETIME = 0, SHD trailing edge to D[9:0] out Output propagation delay, RETIME = 1, DCLK leading edge to D[9:0] out Trailing edge of SHD to leading edge of DCLK Output disable time, OEB rising to D[9:0] and PTDO tristate Output enable time, OEB falling to D[9:0] and PTDO out PTDO propagation delay, RETIME = 0, SHD trailing edge to PTDO out PTDO propagation delay, RETIME=1, DCLK leading edge to PTDO out SYMBOL tPER tCKH tCKL tSHDO TEST CONDITIONS MIN 47.6 19 19 23.0 TYP MAX UNIT ns ns ns ns tDCDO 11.2 ns tSHDC tPEZ 8.3 ns ns tPZE 6.8 ns tSHPT ns tDCPT ns WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 8 WM8170 Product Preview Rev 1.0 CLAMPING CONTROLS CLPENB CLPSWB PBLK CLAMP SWITCH (INTERNAL) VIDEO ISOLATE SWITCH (INTERNAL) tCENE tCEND tCSWE tCSWD tPBIS tPBCO Figure 3 Clamping Controls Timing Diagram Test Characteristics CVDD = AVDD = DVDD = 3.3V, AGND = DGND = CGND = 0V, RISET=15k , TA = 0oC to +70oC, unless otherwise stated. PARAMETER CLPENB enable time CLPENB disable time CLPSWB enable time CLPSWB disable time PBLK isolate time PBLK connect time SYMBOL tCENE tCEND tCSWE tCSWD tPBIS tPBCO TEST CONDITIONS MIN TYP 4.0 4.0 4.4 5.2 MAX UNIT ns ns ns ns ns ns BLCENB INPUT SHD BLCENB tBLCS tBLCH Figure 4 BLCENB Input Timing Diagram Test Characteristics CVDD = AVDD = DVDD = 3.3V, AGND = DGND = CGND = 0V, RISET=15k , TA = 0oC to +70oC, unless otherwise stated. PARAMETER BLCENB setup time to SHD trailing edge BLCENB hold time from SHD trailing edge SYMBOL tBLCS tBLCH TEST CONDITIONS MIN TYP MAX UNIT ns ns WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 9 WM8170 SERIAL INTERFACE tSPER SCK tSSU SDI tSCE SEN SDO tSESD tSCSD tSEW tSEC tSH tSCKL tSCKH Product Preview Rev 1.0 tSCSDZ Figure 5 Serial Interface Timing Diagram Test Characteristics CVDD = AVDD = DVDD = 3.3V, AGND = DGND = CGND = 0V, RISET=15k , TA = 0oC to +70oC, unless otherwise stated. PARAMETER SCK period SCK high SCK low SDI set up time SDI hold time SCK high to SEN high SEN low to SCK high SEN pulse width SEN low to SDO out SCK low to SDO out SCK low to SDO high impedance SYMBOL tSPER tSCKH tSCKL tSSU tSH tSCE tSEC tSEW tSESD tSCSD tSCSDZ TEST CONDITIONS MIN 83.3 37.5 37.5 10 10 20 20 50 9.7 6.7 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns ns ns WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 10 WM8170 Product Preview Rev 1.0 PARALLEL INTERFACE tSTB STB D[9:2] ADC DATA OUT DNA RNW tOPZ tOPD Z tASU tAH tDSU DATA IN tDH Z tSTDO ADC DATA OUT tSTAO DATA OUT ADC DATA OUT ADDRESS IN tADLS tADLH tADHS tADHH Figure 6 Parallel Interface Timing Diagram Test Characteristics CVDD = AVDD = DVDD = 3.3V, AGND = DGND = CGND = 0V, RISET=15k , TA = 0oC to +70oC, unless otherwise stated. PARAMETER RNW low to OP[9:2] Tristate Address setup time to STB low DNA low setup time to STB low STB low time Address hold time from STB high DNA low hold time from STB high Data setup time to STB low DNA high setup time to STB low Data hold time from STB high DNA high hold time from STB high RNW high to OP[9:2] output Data output propagation delay from STB low ADC data out propagation delay from STB high SYMBOL tOPZ tASU tADLS tSTB tAH tADLH tDSU tADHS tDH tADHH tOPD tSTDO tSTAO 0 10 50 10 10 0 10 10 10 0 TEST CONDITIONS MIN TYP MAX 20 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 11 WM8170 SYSTEM INFORMATION Product Preview Rev 1.0 The WM8170 is a complete signal processing and data acquisition system which is designed to interface directly to the analogue output of area array CCDs. The device digitises the video signals from the CCD for subsequent digital processing of the data. The WM8170 can be used in a wide range of CCD-based video applications such as digital still cameras, as shown in Figure 7. CDS PGA Black Level Clamp 10-bit ADC Anti-blooming Reset Gate Bias AREA ARRAY CCD Analogue Video VOUT1 VOUT2 Gamma Correction Colour Balance Data Compression PC Interface 10-bit Parallel Data DIGITAL ASIC LCD DISPLAY WM8170 PIN/DIN SHP SHD DCLK 8-bit Data LCD CONTROLLER 10-bit Data Vertical Drive 3 Horizontal Drive 2 SHP SHD MCLK VERTICAL DRIVER Voltage Translation TIMING GENERATOR MICROCONTROLLER IMAGE MEMORY System Synchronisation Figure 7 Digital Still Camera System Block Diagram WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 12 WM8170 Product Preview Rev 1.0 TYPICAL PERFORMANCE SHD, SHP = 21MHz, PGA gain = 0dB, VRT-VRB = 750mV, RISET = 15K 2 1.5 1 0.5 LSBs 0 -0.5 -1 -1.5 -2 0 256 512 ADC Code 768 1024 Figure 8 WM8170 10-bit DNL Plot WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 13 WM8170 DEVICE DESCRIPTION GENERAL OPERATION Product Preview Rev 1.0 The analogue circuitry within the WM8170 consists of a Sample/Hold (S/H) block, a Programmable Gain Amplifier (PGA), a DC Offset Correction loop, and a 10-bit 21MSPS Analogue to Digital Converter (ADC). The Sample/Hold block takes a Correlated Double Sample (CDS) of the incoming video. The CDS video sample is transferred differentially into the PGA block, which is used to gain the signal to the full dynamic range of the ADC. The PGA is controlled digitally via the management interface. The 10-bit pipeline ADC takes the output from the PGA and converts the analogue voltage into a digital representation of the signal. To correct for DC offsets in the input video, the Sample/Hold block and the PGA, DC offset correction circuitry is provided under the control of external inputs. An analogue correction loop using mixed mode circuitry removes the majority of the DC offset by summing the output of a DAC into the main signal path. An up/down counter controlled from the output of a comparator updates the DAC. The comparator checks the output from the PGA against a voltage representing the target black level. As the analogue correction loop does not correct for DC offsets in either the ADC or the comparator in the feedback loop, a further digital offset is automatically calculated within the digital section following the ADC, which forces the digital output to the previously programmed value. Two auxiliary 8-bit DACs are provided, which can be used within the camera system to control bias voltages to the area CCD, or to provide DC voltages for peripheral camera functions, such as autofocus control. To allow the registers within the WM8170 to be programmed a management interface is provided which allows either serial or parallel control. The interface allows the user to both write to, and read from the internal registers, which eases system debug as values previously programmed can be checked. INPUT SAMPLE AND HOLD, AND VIDEO TIMING The WM8170 includes a Sample/Hold section at its input, which is used to acquire samples from the analogue output of the area array CCD. The Sample/Hold is configured as shown in Figure 9, and can be operated in a basic Sample and Hold mode or in Correlated Double Sampling (CDS) mode. In CDS, the input video reset level is sampled under the control of the signal applied to the SHP digital input and the input video signal level is sampled under the control of the signal applied to the SHD digital input. The Sample/Hold produces a differential voltage output signal, which is passed to the following PGA. Detailed input timing of the Sample/Hold is shown in Figures 10 and 11. Note that there should be no overlap between the SHP and SHD pulses. Any overlap will cause the WM8170 to operate incorrectly. The WM8170 can be programmed via the management interface to accept SHP and SHD inputs as either both positive, or both negative pulses. Control of this function is via the control bit INVSHX. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 14 WM8170 Product Preview Rev 1.0 INPUT BLANKING In some cases the output signals from the CCD can be larger than the input stage of WM8170 could normally handle without overload and saturation. To avoid this situation the Sample/Hold stage is preceded by a pair of analogue switches, which can be used to block the analogue input signals at PIN and DIN from passing to the Sample/Hold stage. These switches are turned on or off by placing a high or low level on the PBLK pin respectively. RESET LEVEL CLAMP OR AC COUPLING The input video can be interfaced via a capacitor to the WM8170 by two methods. A Reset Level Clamp facility is provided which can be used in both Sample and Hold and in CDS modes of operation. The clamp switch is closed if a low level is applied to both CLPENB and CLPSWB digital inputs. The clamp voltage, VCLP, can be programmed via the management interface to be equal to VRB, VMID, or VRT. A typical use of the Reset Level Clamp facility using CDS is shown in Figure 12. Alternatively, the CLPENB and CLPSWB digital inputs can be tied high, which will disable the Reset Level Clamp switch, and the control bit ACINP set. This control bit connects an internal AC coupling resistor to the DIN input, which allows the user to simply AC couple the analogue video signal into the WM8170. If CDS is also used, then any drift on the WM8170 side of the coupling capacitor due to input video DC content will be removed. SHP SHD INVSHX PIN RESET S/H DIFFERENTIAL SIGNAL TO GAIN BLOCK PBLK DIN CLPENB CLPSWB VCLP VMID VCLP VMID 50k ACINP SIGNAL S/H CORRELATED DOUBLE SAMPLING Figure 9 Input Sample/Hold and Reset Level Clamp Block Diagram VIDEO V1 V2 V3 V4 VIDEO SAMPLE, SHD INVSHX=0 REFERENCE SAMPLE, SHP INVSHX=0 Figure 10 Input Sample/Hold Timing, INVSHX = 0 WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 15 WM8170 Product Preview Rev 1.0 VIDEO V1 V2 V3 V4 VIDEO SAMPLE, SHD INVSHX=1 REFERENCE SAMPLE, SHP INVSHX=1 Figure 11 Input Sample/Hold Timing, INVSHX = 1 VIDEO V1 V2 V3 V4 CLPSWB CLPENB RESET LEVEL CLAMP SWITCH ON OFF ON ON Figure 12 Reset Level Clamp Timing WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 16 WM8170 Product Preview Rev 1.0 PROGRAMMABLE GAIN AMPLIFIER The WM8170 contains a Programmable Gain Amplifier (PGA), which precedes the analogue-todigital converter (ADC). The gain of the PGA is set digitally via the management interface to a level which delivers the maximum signal to the input of the ADC without it over ranging, and thus obtaining the maximum dynamic range from the ADC. The gain control on the WM8170 is separated into two sections, a programmable gain section, and a fixed gain section. The programmable gain section is controlled via an 8-bit word written by the management interface, and has a typical range of between 0dB and 28dB. The gain response of the programmable gain section is linear on a logarithmic scale. This means that each LSB increase (or decrease) of digital gain setting represents an equal fraction of a dB (typically 0.11dB) of actual gain increase (or decrease). There is also a fixed gain section, which is programmable to be either 0dB or 6dB. Setting the TIMES2 control bit via the management interface enables this additional gain. Figure 13 shows the typical WM8170 gain response with and without the additional 6dB. PGA GAIN (dB) 34 28 1 2= ES TIM 0 2= ES TIM 6 0 63 127 PGA CODE 191 255 Figure 13 Graph of typical WM8170 Gain Response REFERENCE VOLTAGES All references used on the WM8170 are derived from an internal bandgap reference voltage. The ADC uses two reference voltages, VRT and VRB. The Sample/Hold and PGA use a midrail voltage reference, VMID. The voltage for Reset Level Clamp, VCLP, can be selected to be equal to VRT, VRB or VMID. These four voltages are buffered on-chip and are each available at output pins. Each of these pins should be carefully decoupled with capacitors of the type and size detailed in the Recommended External Components section. The voltage difference between VRT and VRB can be programmed, in order to accommodate different input signal ranges, to two values via the management interface. The WM8170 default condition is VRT-VRB typically 0.5V but can be increased to 0.75V by setting the V375 control bit. Due to the nature of the ADC design, the difference between VRT and VRB is typically half the maximum input signal which the ADC can convert successfully, i.e. if VRT-VRB is 0.75V, then the ADC can accommodate an input signal after the PGA of greater than 1.5V. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 17 WM8170 INPUT SIGNAL AMPLITUDE Product Preview Rev 1.0 The PGA gain setting allows the WM8170 to amplify the input video signal to be equal to the fullscale input of the ADC. The minimum input video signal that can be scaled to the full-scale input of the ADC is defined when the PGA is at the maximum gain. The maximum input video signal that can be scaled to the full-scale input of the ADC is defined when the PGA is at minimum gain. The minimum and maximum video input signal, which the WM8170 can accommodate, is set by a combination of the TIMES2 and the V375 control bits. The input video conditions are summarised in Table 1 MAXIMUM VIN FOR FULL SCALE ADC INPUT PGA GAIN = 00(HEX) 1.0V 1.5V 0.5V 0.75V MINIMUM VIN FOR FULL SCALE ADC INPUT PGA GAIN = FF(HEX) 40mV 60mV 20mV 30mV TIMES2 0 0 1 1 V375 0 1 0 1 Table 1 Input Signal Amplitude Conditions ANALOGUE TO DIGITAL CONVERTER, DEVICE LATENCY AND OUTPUT TIMING The 10-bit resolution ADC uses a pipelined architecture. The latency is the time delay between the video sample (SHD) occurring and the corresponding valid output data being available. There are two possible inputs that control the detailed timing of data output from the WM8170. These are SHD and DCLK. The selection between SHD and DCLK is dependent on the control bit RETIME. If RETIME is set low, then the output data on the D[9:0] pins is referenced to the rising edge of the SHD control input. If RETIME is set high, the output data on the D[9:0] pins is reference to the rising edge of the DCLK clock input. The use of RETIME allows the user to accurately control the output data timing, which can ease the design of the interface between the WM8170 and following digital ASIC, especially for high pixel rate systems. With RETIME set low, the WM8170 latency is equal to eight pixel periods. With RETIME set high, the WM8170 latency is equal to eight pixel periods plus the difference in timing between SHD and DCLK. These two conditions are shown in Figure 14. VIDEO V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 VIDEO SAMPLE, SHD REFERENCE SAMPLE, SHP D[9:0], RETIME=0 8 PIXEL PERIODS DCLK V1 V2 V3 V4 D[9:0], RETIME=1 V1 V2 V3 V4 Figure 14 WM8170 Latency WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 18 WM8170 Product Preview Rev 1.0 SETTING THE MAXIMUM CONVERSION RATE The maximum conversion rate of the ADC, S/H and PGA stages within the WM8170 are directly related to the value of bias current at which the signal path operates. Within limits an increase in bias current allows an increase in maximum conversion rate to be achieved. Inserting a resistor between the ISET pin and AGND sets the value of bias current. The value should be set to that recommended in Table 2 corresponding to the maximum conversion rate at which the device is required to operate. Note that the higher the value of RISET the lower the power consumption of the device will be. RISET 22k 20k 17k 15k MAX. CONVERSION RATE (MSPS) 12 15 18 21 Table 2 RISET vs Maximum Conversion Rate BLACK LEVEL OFFSET CORRECTION CIRCUITRY Unless compensated for, the analogue signal applied to the input of the ADC would contain unacceptably high and variable DC offsets. The offsets consist of the sum of two principal components. These are black level offsets in the output video from the CCD, which can be monitored during optically black pixel phases, and offsets from the amplifiers in the analogue signal path of the WM8170. These offsets would reduce the maximum dynamic range that the ADC can achieve and can vary significantly with time and temperature. Additionally, any DC offsets in the signal path are multiplied by the PGA gain, which can cause the internal amplifiers to limit, particularly if the gain is at a high setting. The DC correction circuitry within the WM8170 has two distinct modes of operation. * * Basic DC correction mode Extended DC correction mode The Basic mode is intended for applications where there is a large difference in the video DC value on adjacent lines in the video stream. The Extended mode is intended for continuous time video applications, where it is necessary to track the video signal DC component without introducing any digital correction noise to the image. This mode is recommended for most of the popular area array CCDs. BASIC DC CORRECTION MODE In the Basic DC correction mode, the DC offset correction is performed in two stages. There is an analogue DC correction loop that removes the majority of the offset, and a digital clamp that removes the rest. Applying a falling edge to the BLCENB digital input pin enables firstly the analogue correction loop and then the digital correction circuitry. This correction circuitry is to be used during periods when optically black pixels are being output from the CCD. The block diagram of the Basic offset correction circuitry is shown in Figure 15. ANALOGUE CORRECTION LOOP The Analogue Correction Loop functions by comparing the output from the PGA during the optically black video period with a DAC output voltage, derived from the ADC reference voltages, which corresponds to a 10-bit code which is programmable between 0 and 255 (dec). This code is the required TARGET for the WM8170 to output for optically black pixels. The output of the comparator, sampled ANDUR times per analogue enable, controls an up/down counter, the contents of which provide the input data to an 8-bit bipolar DAC. The output of this DAC is subtracted from the input of the PGA such that the PGA output becomes closer to the TARGET value programmed. Using this method the majority of any DC offset from either the input video signal, or the signal chain amplifiers is removed. The Analogue Correction Loop does not correct for DC offsets in the ADC or the comparator in the feedback path, and is quantised, in terms of ADC codes, to the resolution of the 8-bit DAC, which changes depending on the actual PGA gain set. Therefore the resulting output code from the ADC during these optically black pixels will not be exactly equal to the TARGET value. The residual error in the black level is corrected in the digital correction circuitry. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 19 WM8170 Product Preview Rev 1.0 DIGITAL CORRECTION CIRCUITRY IN BASIC DC CORRECTION MODE The Digital Correction Circuitry that follows the ADC corrects for any difference between the actual ADC output code and the programmed TARGET value. During the period when the Digital Correction Circuitry is enabled, the circuit calculates the average digital error between the programmed TARGET value and the ADC output code, over a certain number of ADC conversions. This average digital error is subsequently subtracted from all ADC conversions until the Digital Correction Circuitry is enabled again. The number of ADC conversions that the Digital Correction Circuitry calculates the average over is programmable via the management interface. This number is set in the DIGDUR register, and is equal to 2[DIGDUR] pixel periods. DIGITAL GAIN CONTROL Output from Sample and Hold TO OUTPUT PINS D[9:0] + 10 - + PGA COMPARATOR BIPOLAR OUTPUT 8-Bit DAC UP/DOWN COUNTER + - 10-BIT ADC 10 Voltage level corresponding to ADC O/P TARGET code 8-BIT DAC + - ADDER DIVIDE/ HOLD Average error between ADC O/P code and TARGET code during optically black pixels 8 8 TARGET[7:0] DIGITAL ENABLE ANALOGUE ENABLE CONTROL BLCENB ANDUR[6:0] DIGDUR[2:0] STOPDC Figure 15 Basic DC Offset Correction Block Diagram BASIC DC OFFSET CORRECTION INITIATION AND TIMING The overall timing of the Basic DC correction algorithm is shown in Figure 16. The duration of the analogue and digital correction loops are independent. The user must ensure that the overall correction period, which is equal to the analogue loop enable time plus the Digital Correction Circuitry enable time, is no longer than the duration of the optically black pixels output from the CCD. This will prevent the potential error of active video being included in the digital average calculated within the WM8170, which would cause an incorrect error value to be stored. Applying a falling edge to the BLCENB digital input pin enables the Analogue loop and the Digital Correction Circuitry. Once the correction has been initiated, the internal WM8170 control circuitry runs until both the analogue and digital correction enables are complete. All issues associated with latency through the WM8170 have been considered in the internal controller design. OPTICALLY BLACK PIXELS BLCENB ANALOGUE LOOP ENABLED DIGITAL CORRECTION ENABLED PERIOD PROGRAMMABLE PERIOD PROGRAMMABLE Figure 16 Basic DC Correction Algorithm Timing WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 20 WM8170 Product Preview Rev 1.0 The total period (P) of the combined Analogue Correction Loop and Digital Correction Circuitry, measured in Pixel Periods, is given by the following formula: P = ( [ANDUR] x 4 + 2[DIGDUR] ) Where: [ANDUR] is the contents of the Analogue Duration register ANDUR[6:0]. [DIGDUR] is the contents of the Digital Duration register DIGDUR[2:0]. The selection of ANDUR and DIGDUR values is at the discretion of the user, but the following considerations should be made. The internal up/down counter is 8-bit, which covers 256 steps. The counter is incremented/decremented ANDUR times per BLCENB falling edge, which implies that the minimum number of falling edges on BLCENB to guarantee that the analogue loop has reached its final value is 256/ANDUR. In actual use however, the change in DC conditions through the WM8170 will be relatively small, which will mean that the analogue loop will settle to the new value quicker. The value chosen for DIGDUR depends on the number of black pixels available, but a larger value means that any black pixel noise is averaged over a greater number, which will result in a more accurate error value being stored. The analogue DC correction loop error voltage within the WM8170 is not subject to drift because it is derived from a digitally controlled DAC, which implies that once the DC correction circuitry has settled, the correction circuitry can be turned off. This can be achieved by setting the control bit STOPDC via the Management Interface. The correction circuitry should be re-enabled after any write to the PGA register so that DC change due to the different gain is accommodated for. There are two main ways that the DC correction circuitry can be used. The BLCENB can be activated either during the optically black lines at the beginning or end of the CCD output field, or during the optically black pixels at the beginning or end of each video line. Using the first option results in the DC conditions being established before any active video is present, and since completely optically black lines are present large values can be programmed to ANDUR and DIGDUR respectfully. With the second option, smaller values for ANDUR and DIGDUR would have to be used, as the number of black pixels in each line is limited. With both options, it is recommended that the correction circuitry be enabled for one frame of video, and then turned off again. Although the WM8170 only requires a falling edge on BLCENB to initiate the correction circuitry users may input BLCENB signals which are low for the complete duration of the optically black pixels if preferred (this signal format is generally available from CCD timing generator devices). In this case the WM8170 can be programmed to output an error flag on the PTDO pin if the BLCENB input returns to a high state before both the Analogue and Digital Enables are complete. This allows checking that the ANDUR and DIGDUR values programmed to the device will not cause a potential error in the correction circuitry because active video has been included in the internal calculations. See the Programmable Threshold Detect Output section for details of all error flags available. Pixel Periods WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 21 WM8170 EXTENDED DC CORRECTION MODE Product Preview Rev 1.0 The WM8170 device has extended Black Level Correction Circuitry, which make it suitable for continuous video applications. The Black Level Clamp correction circuitry in the WM8170 consists of two main components, an Analogue correction loop which is used to remove the majority of the dc offset using analogue circuit techniques, and a digital filter which can be programmed with different filter responses. Figure 17 shows the Black Level Correction Circuitry in Detail. DIGITAL GAIN CONTROL Output from Sample and Hold VRT IIR ENABLE TO OUTPUT PINS D[9:0] PGA 10-BIT ADC VRB COMPARATOR BIPOLAR OUTPUT 8-Bit DAC UP/DOWN 8 COUNTER + 8-BIT DAC TARGET[7:0] ANALOGUE ENABLE BLCENB INTERNAL ANALOGUE ENABLE CONTROL DIGITAL ENABLE ANDUR[6:0] DIGDUR[3:0] + Average error between ADC O/P code and TARGET code during optically black pixels ADDER DIVIDE + 10 IIR FILTER PRELOAD DATA PRELOAD ENABLE + - R E G 0 1 10 M U X MUX 0 1 SEL STOPDC ENINTBLC Figure 17 Black Level Correction Circuitry In order to control the Correction Circuitry there are two Pulse Generators incorporated within the WM8170. These Pulse Generators and their associated Control Register Bits are shown in Figure 18. This diagram shows all signals associated with the Pulse Generators. External signals are shown with a O, internal register settings with a *. One Pulse Generator is used to generate an internal pulse relative to the falling edge of the BLCENB input. This pulse, called INTBLCENB, is then steered using the Steering Circuitry to be either the enable for the Analogue Correction Circuitry or for the Digital IIR filter. This allows the user to select which lines of the input video frame the Analogue correction loop will be enabled, and for which lines the IIR Filter will be enabled. SHD SHP INTERNAL CLOCK GENERATION BLCENB INTBLCENB PULSE GENERATOR CLPDEL[7:0]* CLPWID[7:0]* PGAUPD* STPANAL* STPIIR* CLK INTBLCENB INTBLCENB STEERING CIRCUITRY ANLINE[7:0]* ANDEL[7:0]* INTERNAL ANALOGUE LOOP ENABLE INTERNAL IIR FILTER ENABLE VD ENVD* LINDEL[11:0]* LINWID[11:0]* CLK HD ENHD* AREA PULSE GENERATOR PIXWID[11:0]* PIXDEL[11:0]* ACON*[1:0]=10 ACON*[1:0]=11 Figure 18 WM8170 Pulse Generators Following a falling edge on the Analogue Correction Loop Enable the internal circuitry is active for ANDUR*4 pixels, which allows the majority of the DC error to be removed by the analogue circuitry. After this has completed the remaining offset is removed by a digital clamp that averages the ADC error from the programmed TARGET value for 2DIGDUR pixels and subsequently subtracts that WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 22 WM8170 Product Preview Rev 1.0 averaged error from all ADC conversions until the Analogue Black Level Correction circuitry is enabled again. The calculated average is also used to preload the Digital IIR Filter, so that there are no discontinuities in the correction value applied when the IIR Filter is enabled. For further details of the operation of the Analogue Correction Loop, ANDUR and DIGDUR, refer to the Basic DC Correction Mode section. The IIR Filter allows the WM8170 to track relatively slow changes in the input video DC content across a single frame of input video. The main advantage of the IIR Filter approach is to allow the number of pixels over which the digital correction value is calculated to be much larger than the number of black pixels available on a single line. This results in a stable correction value that does not vary on a line to line basis due to the RMS noise during the black pixels. The WM8170 also contains a second Pulse Generator that can be programmed to complement either the Analogue Loop Enable or the IIR Filter Enable as required. ENABLING THE HD AND VD INPUTS TO THE WM8170 To enable the use of all the Black Level Control Circuitry within the WM8170, both the Vertical Drive (VD) and the Horizontal Drive (HD) control signals are required from the CCD Timing Generator device. There are two dual mode pins on the WM8170 which are programmed via the Management Interface register bits ENVD and ENHD. Details of the dual mode pins are covered in the Tables 3 and 4: ENVD 0 1 FUNCTION Pin 30 is PDB (Power Down Bar) Input Pin 30 is VD (Vertical Drive) Input Table 3 ENVD control bit operation ENHD 0 1 FUNCTION Pin 26 is PBLK (Video Blocking) Input Pin 26 is HD (Horizontal Drive) Input Table 4 ENHD control bit operation When ENVD is set, PDB is held high internally in the WM8170. The Power Down Function remains available via the Management Interface. When ENVD is reset, the internal circuitry requiring Vertical Drive will not function. When ENHD is set, PBLK is held high internally in the WM8170. The Video Blocking function is not available in this mode. When ENHD is reset, the internal circuitry requiring Horizontal Drive will not function. INTERNAL BLACK LEVEL CLAMP ENABLE The control for the Analogue Correction Loop can be programmed to be either the BLCENB pin, or the INTBLCENB signal under control of the register bit ENINTBLC. To benefit from the extended Black Level Control Circuitry within the WM8170 this bit must be set. Table 5 shows the operation of the ENINTBLC control bit. ENINTBLC 0 1 FUNCTION Analogue Loop Enable is controlled by BLCENB pin directly. Analogue Black Level Enable is controlled by the signals generated by the INTBLCENB Pulse Generator. Table 5 ENINTBLC control bit operation WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 23 WM8170 BLCENB CONTROLLED PULSE GENERATOR Product Preview Rev 1.0 The internal master clock derived from the SHP and SHD digital inputs clocks the INTBLCENB pulse generator. The pulse generator is controlled by the BLCENB input, and is used to generate an internal pulse that is timed relative to the falling edge of the BLCENB input. This pulse can be selectively used to control either the analogue control loop or the IIR filter. The Pulse Steering Circuit is reset by a falling edge on the VD input so that the user can determine which video lines will enable the Analogue Correction Circuitry and which will enable the IIR Filter. Enabling the analogue DC correction circuitry is required to remove the majority of the offset from the incoming video. The value of this offset at the input to the ADC is dependent on the gain of the PGA, hence the analogue DC correction circuitry should be enabled either at the beginning of each frame, or only when the PGA gain is changed. Figure 19 shows the generation of the INTBLCENB pulse relative to the falling edge of the BLCENB pin. There are two Management Interface registers that control the generation of the INTBLCENB signal. CLPDEL[7:0] defines the delay in pixel periods from the falling edge of BLCENB pin to the falling edge of the INTBLCENB signal. The delay is equal to CLPDEL+1 pixels. CLPWID[7:0] defines the width of the INTBLCENB signal. The width of the signal is CLPWID pixels. SHD SHP MCLK (Internal) BLCENB INTBLCENB CLPDEL+1 PIXELS CLPWID PIXELS EDGE WHICH SAMPLES BLCENB Figure 19 Generating the INTBLCENB Pulse STEERING THE INTBLCENB SIGNAL Figure 20 shows how the INTBLCENB signal can be steered to either the Analogue Loop Enable, or to the IIR Filter Enable. There are two Management Interface Registers which control how the INTBLCENB signal is steered. ANDEL[7:0] defines the delay in INTBLCENB pulses from the falling edge of the VD input. The INTBLCENB pulses during this period are steered to the IIR Filter. The delay is equal to ANDEL. ANLINE[7:0] is defines the number of INTBLCENB pulses steered to the Analogue Loop Enable. The number is equal to ANLINE. The INTBLCENB pulse is steered to the IIR Filter whenever it is not used for the Analogue Loop Enable. VD BLCENB INTBLCENB GENERATED RELATIVE TO FALLING EDGE OF BLCENB INTBLCENB ANALOGUE ENABLE IIR FILTER ENABLE PROGRAMMABLE DELAY IN INTBLCENB PULSES = ANDEL PROGRAMMABLE NUMBER OF INTBLCENB PULSES = ANLINE Figure 20 Steering the INTBLCENB Signal The steering circuitry allows the user to select which lines of the input video the analogue DC correction loop will be enabled for, and to place these lines in a non viewed section of the frame. The lines which have the analogue DC correction loop enabled will be subject to line noise due to the correction value that is being applied only having been calculated over only a small number of pixels. The effect of line noise during the analogue loop enables can be minimized if a large number of pixels are used to calculate the digital average. This can be achieved if the analogue loop is enabled during the optically black lines at the beginning of a video frame. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 24 WM8170 CONTROLLING THE BLACK LEVEL CLAMP CIRCUITRY Product Preview Rev 1.0 There are three Management Interface control bits that are associated with the INTBLCENB pulse generator, STPANAL, STPIIR, and PGAUPD. Their function is shown in Tables 6, 7 and 8: STPANAL 0 1 FUNCTION Allows the INTBLCENB signal to be steered to the Analogue DC correction Loop. Disables the INTBLCENB signal from being steered to the Analogue DC correction Loop. The INTBLCENB pulses that would have been steered to the Analogue Enable are steered to the IIR Filter enable instead. Table 6 STPANAL control bit operation STPIIR 0 1 FUNCTION Allows the INTBLCENB signal to be steered to the IIR Filter Disables the INTBLCENB signal from being steered to the IIR Filter Table 7 STPIIR control bit operation PGAUPD 0 1 FUNCTION The INTBLCENB signal will be steered to the Analogue DC correction loop as programmed on every frame. The INTBLCENB signal will only be steered to the Analogue DC correction loop as programmed if the PGA gain register has been written to. Table 8 PGAUPD control bit operation The PGAUPD control bit enables the internal WM8170 circuitry to steer the INTBLCENB signals to the Analogue Control Loop for one frame only following a write to the PGA Gain register. The INTBLCENB signals will be steered to the IIR Filter on all other frames. This implies that there will only be ANLINE lines subject to line noise, only for a single video frame, and only if the PGA gain register has been written to. If the PGAUPD control bit has not been set, then the INTBLCENB signals will be steered to the Analogue Control Circuitry on every frame. SETTING THE IIR FILTER COEFFICIENT Writing to the COEFF register controls the IIR filter response. Table 9 shows the coefficients available on the WM8170, and the effective attenuation of the RMS noise during the optically black pixels that will be present on the calculated error. COEFF REGISTER VALUE 000 001 010 011 100 101 110 111 IIR FILTER COEFF 5 6 7 8 9 10 11 12 RMS Noise Attenuation (dB) 18.0 21.0 24.1 27.1 30.1 33.1 36.1 39.1 RMS Noise Attenuation (Times) 7.9 11.3 16.0 22.6 32.0 45.2 64.0 90.5 10% 72 146 293 588 1177 2356 4714 9430 1.0% 334 673 1352 2709 5423 10853 21711 43427 0.1% 2307 4651 9339 18714 37466 74969 149976 299988 Table 9: IIR Filter Coefficients The 10%, 1.0% and 0.1% columns give the number of pixels that the IIR filter has to be enabled for to achieve the percentage settling, i.e. if the input has a 100LSB step then the number of pixels required for the filter to settle to 1LSB is equal to the number in the 1% column. For example, if the filter coefficient is set to 7, and the input has a 100LSB step, it will require 1352 enabled pixels for the filter to settle to 1LSB of the final error value. There is a trade-off between the number of pixels required for the filter to settle, and the RMS noise attenuation achieved on the calculated error value. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 25 WM8170 INTERNAL AREA PULSE GENERATOR Product Preview Rev 1.0 In addition to the INTBLCENB pulse generator described above, the WM8170 includes an independent pulse generator which can be use to define any area within the video frame. The output of the Area Pulse Generator can be used either independently of the INTBLCENB pulse (if the BLCENB pulse generator is turned off using the STPANAL and STPIIR control bits), or to define additional areas where the user wishes either the Analogue Control Loop or the IIR filter to operate. This pulse generator works in a similar way to the pulse generator described above, but uses the Vertical Drive (VD) and Horizontal Drive (HD) inputs, along with the Master Clock, to allow the user to define any area within the active video signal. The horizontal area enable operates as shown in Figure 21. The Management Interface registers PIXDEL[11:0] and PIXWID[11:0] are used to define the pulse. The horizontal Area Pulse will have a delay of PIXDEL+1 pixels from the falling edge of the HD input, and will be PIXWID pixels wide. SHD SHP MCLK (Internal) HD INTERNAL HORIZONTAL AREA PIXDEL+1 PIXELS PIXWID PIXELS EDGE WHICH SAMPLES HD Figure 21 Generating the Horizontal Area Pulse The vertical area enable operates as shown in Figure 22. The Management Interface registers LINDEL[11:0] and LINWID[11:0] are used to define the pulse. The Vertical Area Pulse will have a delay of LINDEL HD pulses from the falling edge of the VD input, and will be LINWID HD pulses wide. VD HD INTERNAL VERTICAL AREA LINDEL HD LINWID HD EDGE WHICH COUNTS ARE REFERRED TO Figure 22 Generating the Vertical Area Pulse The logical combination of the active low, horizontal area pulse and the active low, vertical area pulse is used to define the area of the input video required. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 26 WM8170 USING THE AREA PULSE GENERATOR Product Preview Rev 1.0 The area defining pulse can be used under control of the ACON register bits to enable various functions as detailed in the Table 10: ACON1 0 0 ACON0 0 1 FUNCTION Area define signal turned off. Area define signal used to update the internal register which holds the error calculated by the IIR filter. In other conditions the internal register which holds the error calculated by the IIR filter is enabled whenever the IIR filter is enabled. Area Define signal used to enable the Analogue DC Correction circuitry in addition to the analogue enable generated from the INTBLCENB pulse generator. Area Define signal is used to enable the IIR filter in addition to the IIR filter enable generated from the INTBLCENB pulse generator. 1 0 1 1 Table 10 ACON[1:0] control bits operation VIEWING THE INTERNALLY GENERATED PULSES ON THE PTDO PIN For system debug purposes all the internally generated pulses can be multiplexed onto the PTDO signal pin, under control of the PTDO[2:0] register bits as described in the Table 11: PTDO2 0 0 0 0 PTDO1 0 0 1 1 PTDO0 0 1 0 1 PTDO PIN FUNCTION Programmable Threshold Detect Output ADC Out of Range Signal Clip 1 Error - Digital correction error (ADC output is outside the digital correction range) BLCENB Error - caused by BLCENB going high before the internal DC offset correction circuitry associated with the analogue DC correction loop has finished Active low going, analogue DC loop enable pulse Active low going, IIR enable pulse Active low going, Area Define pulse Reserved for Test Purposes 1 1 1 1 0 0 1 1 0 1 0 1 Table 11 PTDO[2:0] control bits operation WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 27 WM8170 PROGRAMMABLE THRESHOLD DETECT OUTPUT Product Preview Rev 1.0 The Programmable Threshold Detect Output, (PTDO), primary function is to indicate to the user when the ADC output has exceeded a value programmed into the THRES[9:0] registers via the Management Interface. The PTDO output will output a high state, which is aligned to the output data, if the ADC output exceeds the programmed value. Typically this pin would be used in conjunction with external gain calibration algorithms to set the PGA gain. The PTDO output can also be used to indicate a number of system error flags which are available to the user. These flags are multiplexed onto the PTDO pin under control of the Management Interface. An error can be flagged if the pixel data during the black pixels is outside the correction range of the logic within the WM8170, or if the BLCENB pin has returned high before both the analogue and digital DC correction circuitry has completed their tasks. An error can also be flagged if the output from the ADC is out of range, i.e. the ADC output code is trying to exceed 3FF(hex), or be less than 0(hex). The error flag can be programmed to be output on the PTDO pin under control of the register bits PTDO[1:0]. AUXILIARY DIGITAL TO ANALOGUE CONVERTERS The WM8170 includes two independent 8-Bit Digital to Analogue Converters. Their analogue outputs are available at pins VOUT1 and VOUT2 respectively. Their output voltages are controlled in two ways. The maximum output voltage from the DACs can be independently set to be either AVDD or AVDD/2 under control of the AUX1X1 and AUX2X1 control bits. Each DAC can then be programmed to one of 256 codes by the 8-bit contents of the Auxiliary DAC registers defined in the register map shown in Table 15. These DACs can be used to trim CCD control voltages such as the anti-blooming or reset gate bias voltages, or used within the camera system for features such as auto-focus. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 28 WM8170 Product Preview Rev 1.0 MANAGEMENT INTERFACE The WM8170 includes an easy-to-use and comprehensive Management Interface that allows the user to write to and read from on-board registers and thus control all the digitally programmable features of the device. The Management Interface can be configured to operate in either Parallel or Serial Mode by setting the Parallel Not Serial (PNS) pin high or low respectively. Serial Mode is recommended for real time video applications because writing and reading from the device can be carried out at any time. If Parallel Mode is used, writing and reading must be performed within areas of inactive video to prevent valid ADC output data from being replaced with the Management Interface data. MANAGEMENT INTERFACE CONFIGURATION The pins used to control the Management Interface are described in Table 12. The timing for writing in Serial and Parallel Mode is shown in Figures 23 and 24 respectively. Selected registers can also be read via the interface thus allowing stored values to be checked by the user. The timing for reading in Serial and Parallel Mode is shown in Figures 25 and 26 respectively. PIN NAME PNS SEN/STB SDI/DNA SCK/RNW SDO D2-D9 SERIAL MODE FUNCTION Set Low to indicate Serial Mode Serial interface ENable, active High Serial Data Interface Serial interface Clock Serial Data Out Not Used PARALLEL MODE FUNCTION Set High to indicate Parallel Mode Parallel interface STrobe, active Low Data Not Address input Read Not Write input Not Used Parallel data I/O pins Table 12 Management Interface Pins and Functions SCK SDI x a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 SEN ADDRESS DATA WORD Figure 23 Writing in Serial Mode SCK X 1 a4 a3 a2 a1 a0 X X X X X X X X X SDI ADDRESS SEN DATA WORD SDO d7 d6 d5 d4 d3 d2 d1 d0 OUTPUT DATA WORD Figure 24 Reading in Serial Mode WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 29 WM8170 STB D[9:2] Z Z Product Preview Rev 1.0 ADDRESS DATA DNA RNW Figure25 Writing in Parallel Mode STB Z Z D[9:2] ADDRESS NORMAL OUTPUT DATA READ DATA DNA RNW Figure 26 Reading in Parallel Mode POWER DOWN CONTROL The WM8170 includes a separate power down pin, PDB. When this pin is taken low the whole device is powered down and all internal registers maintain their currently programmed value. Setting the PD0 bit in the Power Down 1 register can perform a similar power down operation. These two global power downs are logically OR' d. In addition to the above power down facilities the WM8170 contains seven other selective power downs of individual sections of the device. Setting the appropriate bit in the Power Down 2 register, as described in the Device Configuration section of this data sheet, will power down the particular part of the circuit. These bits are logically ANDed so that any combination of the available device sections can be powered down simultaneously WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 30 WM8170 Product Preview Rev 1.0 POWER SUPPLIES This datasheet describes the WM8170 for use in a complete 3.3V system. The performance and characteristics will differ for the WM8170 if a 5V supply is required. If 5V supplies are required, contact Wolfson Microelectronics Ltd. for further detailed parametric information. The WM8170 includes several power supply pins, each of which routes power to particular parts of the device circuitry. It is important to note the circuit sections of the device, which are connected to the various supply pins. This is summarised in Table 13. The WM8170 can operate with all supply pins connected to 5V or with all supply pins connected to 3.3V. It can also operate with all analogue supply pins at 5V and the individual digital supply pins connected to a combination of 5V and 3.3V. The set of allowable combinations of supply pin connections is shown in Table 14. All AVDD, CVDD and DVDD1 pins should be maintained at the same supply voltage. The other supplies can be at any combination of either 5V or 3.3V. SUPPLY NAME AVDD1 AVDD2 AVDD3 CVDD DVDD1 DVDD2 DVDD3 DVDD4 ADC Main analogue signal path Reference and bias generator Clock generator circuitry Internal logic and level shifters BLCENB, CLPENB, CLPSWB, PBLK, SHD, SHP PDB, NRESET, SCK/RNW, SEN/STB, PNS, SDI/DNA, OEB, DCLK, SDO D0-D9, PTDO CIRCUIT SECTIONS CONNECTED TO Table 13 Supply Pins Vs Device Circuit Sections Connected NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AVDD1, AVDD2, AVDD3, CVDD, DVDD1 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 5V 5V 5V 5V 5V 5V 5V 5V DVDD2 3.3V 3.3V 3.3V 3.3V 5V 5V 5V 5V 3.3V 3.3V 3.3V 3.3V 5V 5V 5V 5V DVDD3 3.3V 3.3V 5V 5V 3.3V 3.3V 5V 5V 3.3V 3.3V 5V 5V 3.3V 3.3V 5V 5V DVDD4 3.3V 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V 5V 3.3V 5V Table 14 Supply Pins vs Supply Voltages - Allowable Combinations GROUND AND POWER SUPPLY PIN CONNECTIONS As detailed above, each of the power supply and ground pins of the WM8170 is allocated to a particular section of the overall device circuitry. It is important that the use of ground and power planes on any printed circuit board layout should take account of this fact. See Figure 27 for Recommended Device Decoupling. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 31 WM8170 DEVICE CONFIGURATION REGISTER MAP Product Preview Rev 1.0 The register map is shown in Table 15. In Serial Mode the contents of address location Address Table 15 Register Table WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 32 WM8170 Product Preview Rev 1.0 CONTROL BIT TABLE CONTROL BITS SOFTWARE RESET (000001) A write to this register will force all registers to return to their default state. SET UP REGISTER 1 (000010) VCLP[1:0] Controls the VCLP voltage output. VCLP1 VCLP0 VCLP PIN 0 0 VRB 0 1 VMID 1 0 VRT 1 1 Reserved Enables the AC coupling resistor between DIN and VMID. ACINP 0 No AC coupling resistor 1 AC coupling resistor Enables the invert on SHD/SHP. INVSHX 0 No invert, SHD / SHP active low 1 Invert, SHD / SHP active high Enables additional 6dB gain in PGA. TIMES2 0 No additional 6dB gain 1 Additional 6dB gain Allows the WM8170 to accept positive going video. Default input video is negative. POSVID 0 Input video negative going (Default) 1 Input video positive going Enables or disables both the analogue and digital DC correction circuitry. STOPDC 0 DC offset correction circuitry enabled 1 DC offset correction circuitry disabled Enables the retiming of the digital outputs with DCLK. RETIME 0 No retiming 1 Output data retimed Digitally inverts the D[9:0] outputs. INVDIG 0 No invert 1 Outputs inverted Selects the signal output onto the PTDO Pin. PTDO2 PTDO1 PTDO0 PTDO PIN 0 0 0 Threshold detect output 0 0 1 Out of range signal 0 1 0 Clip1 error - digital correction error (ADC output is outside the digital correction range). 0 1 1 BLCENB error - caused by BLCENB going high before the internal DC offset correction circuitry has finished. 1 0 0 Active low going, analogue DC loop enable pulse 1 0 1 Active low going, IIR enable pulse 1 1 0 Active low going, Area Define Pulse 1 1 1 Reserved for Test Purposes DESCRIPTION ACINP INVSHX TIMES2 POSVID STOPDC SET UP REGISTER 2 (000011) RETIME INVDIG PTDO[2:0] WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 33 WM8170 CONTROL BITS BLACK LEVEL TARGET (000100) TARGET[7:0] PGA GAIN (000101) GAIN[7:0] Controls the PGA gain. 00hex is minimum gain FFhex is maximum gain Target value for the black level. DESCRIPTION Product Preview Rev 1.0 DIGITAL DURATION (000110) DIGDUR[3:0] Digital correction duration: number of ADC conversion that are used to calculate the average. DIGDUR3 DIGDUR2 DIGDUR1 DIGDUR0 Durations 0 0 0 0 1 ADC conversion 0 0 0 1 2 ADC conversions 0 0 1 0 4 ADC conversions 0 0 1 1 8 ADC conversions 0 1 0 0 16 ADC conversions 0 1 0 1 32 ADC conversions 0 1 1 0 64 ADC conversions 0 1 1 1 128 ADC conversions 1 0 0 0 256 ADC conversions 1 0 0 1 512 ADC conversions 1 0 1 0 1024 ADC conversions 1 0 1 1 2048 ADC conversions 1 1 0 0 2048 ADC conversions 1 1 0 1 2048 ADC conversions 1 1 1 0 2048 ADC conversions 1 1 1 1 2048 ADC conversions Controls the duration of the analogue loop enable - i.e. it represents the number of times that the up-down counter will be clocked per falling edge of the BLCENB input. ANALOGUE DURATION (000111) ANDUR[6:0] THRESHOLD DETECT LSB / MSB (001001/10) THRES[9:0] Threshold detect value. If the corrected ADC output data is greater than the THRES[9:0] then PTDO will be high. (Note PTDO[1:0] must be 00bin). Note THRES[9:0] is split into two registers, THRES[9:8] and THRES[7:0]. POWER DOWN 1 (001011) PDA PD[7:0] Global power down, OR'd with PDB pin Controls the analogue power downs. Note this is split over 2 registers (0 - block enabled, 1 - block powered down). PD0 PD1 PD2 PD3 PD4 PD5 AUXILIARY DAC 1 AUX1DAC[7:0] (001101) Auxiliary 1 DAC value S/H, PGA and the analogue correction loop power down VMID and VCLP power down. VRT and VRB power down. ADC only power down. AUX2DAC power down AUX1DAC power down POWER DOWN 2 (001100) AUXILIARY DAC 2 (001110) AUX2DAC[7:0] Auxiliary 2 DAC value. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 34 WM8170 CONTROL BITS AUX DAC CONTROL (010000) AUX1X1 Auxiliary DAC1 scaling factor. AUX1X1 0 TIMES2 1 TIMES1 Auxiliary DAC2 scaling factor. AUX2X1 0 TIMES2 1 TIMES1 DESCRIPTION Product Preview Rev 1.0 AUX2X1 DC CORRECT CONTROL (001111) ENINTBLC Used to select between the BLCENB pin and the INTBLCENB pulse for the Analogue Loop Enable ENINTBLC 0 BLCENB pin controls the Analogue Correction Loop 1 INTBLCENB pulse controls the Analogue Correction Loop Changes pin 26 between PBLK and HD functions ENHD 0 Pin 26 is PBLK function 1 Pin 26 is HD function Changes pin 30 between PDB and VD functions ENVD 0 Pin 30 is PDB function 1 Pin 30 is VD function Update the analogue control loop after PGA writes only PGAUPD 0 Enable INTBLCENB Pulse to Analogue Loop on every frame. 1 Enable INTBLCENB Pulse to Analogue Loop only after PGA Register has been written to. Stops the INTBLCENB signal from enabling the analogue control loop STPANAL 0 INTBLCENB can be steered to the Analogue Loop Enable 1 INTBLC will be prevented from being steered to the Analogue Loop Enable, and will be used for the IIR Filter Enable instead. Stops the INTBLCENB signal from enabling the IIR filter STPIIR 0 INTBLCENB can be steered to the IIR Filter Enable 1 INTBLC will be prevented from being steered to the IIR Filter Enable Used to control the function of the Area Pulse Generator ACON1 ACON0 Area define signal turned off. 0 0 0 1 Area define signal used to update the internal register which holds the error calculated by the IIR filter. In other conditions the internal register which holds the error calculated by the IIR filter is enabled whenever the IIR filter is enabled. Area Define signal used to enable the Analogue DC Correction circuitry in addition to the analogue enable generated from the INTBLCENB pulse generator. Area Define signal is used to enable the IIR filter in addition to the IIR filter enable generated from the INTBLCENB pulse generator. ENHD ENVD PGAUPD STPANAL STPIIR ACON[1:0] 1 0 1 1 WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 35 WM8170 CONTROL BITS ANALOGUE LOOP ENABLE DELAY (010001) ANDEL[7:0] DESCRIPTION Product Preview Rev 1.0 Sets the delay in INTBLCENB pulses before the Steering circuit steers the INTBLCENB pulse to the Analogue Loop Enable. Sets the number of INTBLCENB pulses to steer to the Analogue Loop Enable. Sets the delay in pixels from the falling edge of BLCENB for the INTBLCENB pulse. Sets the width of the INTBLCENB pulse. Sets the delay in HD pulses from the falling edge of VD for the vertical Area Pulse. Least significant 8 bits. Sets the delay in HD pulses from the falling edge of VD for the vertical Area Pulse. Most significant 4 bits. Selects ADC reference voltage V375 VRT-VRB 0 0.5V 1 0.75V ANALOGUE LOOP ENABLE WIDTH (010010) ANLINE[7:0] CLPDEL[7:0] CLPWID[7:0] LINDEL[7:0] LINDEL[11:8] V375 INTBLCENB PULSE GENERATOR DELAY (010011) INTBLCENB PULSE GENERATOR WIDTH (010100) AREA PULSE GENERATOR LINE DELAY LSB (010101) AREA PULSE GENERATOR LINE DELAY MSB (010110) REFERENCE SELECT (010111) AREA PULSE GENERATOR LINE WIDTH LSB (011000) LINWID[7:0] Sets the width in HD pulses of the vertical Area Pulse. Least significant 8 bits. AREA PULSE GENERATOR LINE WIDTH MSB (011001) LINWID[11:8] PIXDEL[7:0] PIXDEL[11:8] PIXWID[7:0] PIXWID[11:8] COEFF[2:0] Sets the width in HD pulses of the vertical Area Pulse. Most significant 4 bits. Sets the delay in pixels from the falling edge of HD for the horizontal Area Pulse. Least significant 8 bits. Sets the delay in pixels from the falling edge of HD for the horizontal Area Pulse. Most significant 4 bits. Sets the width in pixels of the horizontal Area Pulse. Least significant 8 bits. Sets the width in pixels of the horizontal Area Pulse. Most significant 4 bits. Sets the IIR Filter Coefficient COEFF2 COEFF1 COEFF0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 AREA PULSE GENERATOR HORIZONTAL PIXEL DELAY LSB (011010) AREA PULSE GENERATOR HORIZONTAL PIXEL DELAY MSB (011011) AREA PULSE GENERATOR HORIZONTAL WIDTH LSB (011100) AREA PULSE GENERATOR LINE HORIZONTAL WIDTH MSB (011101) IIR FILTER COEFFICIENT (011110) Filter Coefficient 5, RMS Noise Attenuation 18.0dB 6, RMS Noise Attenuation 21.0dB 7, RMS Noise Attenuation 24.1dB 8, RMS Noise Attenuation 27.1dB 9, RMS Noise Attenuation 30.1dB 10, RMS Noise Attenuation 33.1dB 11, RMS Noise Attenuation 36.1dB 12, RMS Noise Attenuation 39.1dB REVISION NUMBER (011111) REV[7:0] The device revision number. This is ASCII representation of the device revision number i.e. ` B, C etc' as A, , a seven bit number, e.g.: `41'= A, ` = B, etc. 42' WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 36 WM8170 Product Preview Rev 1.0 APPLICATIONS RECOMMENDATIONS SETTING UP THE WM8170 FOR BLACK LEVEL CORRECTION The WM8170 requires that certain register bits are set in order to get the best performance from the WM8170, and so that all the Black Level Clamp features within the device are enabled. To help with this task, the following is a list of register bits that must be set, and what function the bit performs. 1. Set Reference Select, Address 17Hex (010111Bin) to 01Hex. V357=1: 2. This will set the VRT-VRB voltage to 0.75Volts, which will give the best analogue performance from the WM8170. Set DC Correct Control, Address 0FHex (011111Bin) to 07Hex. ACON[10]=00 STPIIR=0 STPANAL=0 PGAUPD=0 ENVD=1 ENHD=1 ENINTBLC=1 Area Pulse Generator turned off. The INTBLCENB pulse can be steered to the IIR Filter The INTBLCENB pulse can be steered to the Analogue Loop Enable. Steer the INTBLCENB pulse to the Analoguee Control Loop on every frame. Enable the Vertical Drive CCD timing signal (VD) operation. VD needs to be connected to the PDB/VD pin (No. 30). Enable the Horizontal Drive CCD timing signal (HD) operation. HD needs to be connected to the PBLK/HD pin (No. 26). Control the Analogue Black Level Clamp from the INTBLCENB steering circuitry rather than from the BLCENB pin. 3. Set Analogue Enable Delay, Address 11Hex (010001Bin) to 04Hex. ANDEL[7:0]=04 The Analogue Correction circuitry will be enabled 4 lines after the falling edge of the VD signal. 4. Set Analogue Enable Width, Address 12Hex (010010Bin) to 06Hex. ANLINE[7:0]=06 The Analogue Correction Circuitry will be enabled for 6 lines. 5. Set INTBLCENB Delay, Address 13Hex (010011Bin) to 10Hex. CLPDEL[7:0]=10 The INTBLCENB pulse will be enabled 17 (16+1) pixels after the falling edge of the BLCENB pin. 6. Set INTBLCENB Width, Address 14Hex (010100Bin) to 10Hex. LINDEL[7:0]=10 The INTBLCENB pulse will be enabled for 16 pixels. 7. Set IIR Filter Coefficient, Address 1EHex (011110Bin) to 04Hex. COEFF[2:0]=04 IIR Filter Coefficient set to 9, giving 30.1dB attenuation of the noise during the optically black pixels. This is the middle Filter Coefficient. The device is now set up to use the internal black level circuitry. The Area Circuitry is not enabled or programmed at this time. To enable debug of the signals, the PTDO pin has to be programmed and monitored with an oscilloscope. The oscilloscope should display VD, HD, BLCENB, PTDO, SHD, SHP. The oscilloscope should be triggered by VD. 8. Set Set-Up Register 2, Bits 7, 6, and 5 to 100Bin. PTDO[2:0]=100 The Analogue DC Loop Enable Pulse is output onto the PTDO pin. The oscilloscope should show 6 negative going INTBLCENB pulses, occurring 4 lines after the falling edge of the VD signal. Each INTBLCENB pulse will be 16 pixels wide, occurring 17 pixels after the falling edge of the BLCENB signal. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 37 WM8170 9. Set Set-Up Register 2, Bits 7, 6 and 5 to 101Bin. PTDO[2:0]=101 Product Preview Rev 1.0 The IIR Filter Enable is output onto the PTDO pin. The oscilloscope should show the INTBLCENB pulses on all lines except those where there was an Analogue DC Loop Enable Pulse, i.e. for the 6 lines occurring 4 lines after the falling edge of the VD signal. The Analogue Loop Enable and IIR Filter Enable, and the INTBLCENB pulses should now be matched to the CCD being used, by adjusting the register addresses 11Hex, 12Hex, 13Hex, 14Hex and 1EHex (numbers 3-7 Above). WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 38 WM8170 Product Preview Rev 1.0 RECOMMENDED EXTERNAL COMPONENTS DEVICE DECOUPLING The WM8170 contains a high speed 10-bit ADC and wide bandwidth signal amplifiers that are sensitive to noise on supply pins, reference pins and elsewhere. Therefore particular attention should be paid to the decoupling of the WM8170 to prevent unwanted noise from entering the signal path. Figure 27 and Table 16 show the recommended decoupling capacitors and ground connections. Note that the analogue and digital ground pins are each connected to their respective separate analogue and digital ground return paths. Each analogue supply pin is decoupled to the analogue ground with a parallel combination of tantalum and ceramic capacitors. Each digital supply pin is decoupled to the digital ground with the same parallel capacitor combination. For optimum performance each parallel capacitor combination should be connected as close to the particular supply pin as is physically possible. The careful use of separate analogue and digital ground planes can help to prevent coupling of digital noise into the sensitive analogue sections of the internal device circuitry. The AGND and DGND connections should be star-pointed as close to the WM8170 as possible. DVDD DGND FB1 C1 C2 FB2 C3 C4 48 47 D3 46 D2 45 D1 44 D0 43 CGND 42 CVDD 41 VOUT2 40 VOUT1 39 DVDD1 38 37 36 35 34 33 32 31 30 29 28 27 26 25 FB3 C5 C6 D4 1 2 3 4 5 6 7 8 9 D5 DGND2 SCK/RNW DCLK SEN/STB SDI/DNA SDO DVDD3 NRESET DVDD4 D6 D7 RNR D8 D9 PTDO WM8170 OEB PDB/VD CNR PNS DGND1 BLCENB PBLK/HD CLPSWB SHP DVDD2CLPENB AGND1 AVDD1 AVDD FB4 C7 C8 C9 C10 10 11 12 AVDD3 VCLP ISET VRT VRB VMID AGND2 DIN PIN AVDD2 SHD 13 14 15 16 17 18 19 20 21 22 23 24 AGND RISET C13 C11 C15 C16 CIN C14 Figure 27 WM8170 External Components WOLFSON MICROELECTRONICS LTD INPUT VIDEO C12 PP Rev 1.0 March 2000 39 WM8170 COMPONENT REFERENCE FB1 FB2 FB3 FB4 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 CIN CNR RNR RISET Table 16 Device Decoupling Components 10F 0.1F 10F 0.1F 10F 0.1F 10F 0.1F 10F 0.1F 1F 0.1F 1F 0.1F 1F 0.1F SUGGESTED VALUE Product Preview Rev 1.0 DESCRIPTION Optional ferrite bead Optional ferrite bead Optional ferrite bead Optional ferrite bead Decoupling to DGND for pin 39(DVDD1), pin 33(DVDD3) and pin 23(DVDD2) Decoupling to DGND for pin 39(DVDD1), pin 33(DVDD3) and pin 23(DVDD2) Decoupling to DGND for pin 42(CVDD) Decoupling to DGND for pin 42(CVDD) Decoupling to DGND for pin 3(DVDD4) Decoupling to DGND for pin 3(DVDD4) Decoupling to AGND for pin 10(AVDD1), pin 11(AVDD3) and pin 20(AVDD2) Decoupling to AGND for pin 10(AVDD1), pin 11(AVDD3) and pin 20(AVDD2) Decoupling to AGND for pin 12(VCLP) Decoupling to AGND for pin 12(VCLP) Decoupling to AGND for pin 14(VRT) Decoupling to AGND for pin 14(VRT) Decoupling to AGND for pin 15(VRB) Decoupling to AGND for pin 15(VRB) Decoupling to AGND for pin 16(VMID) Decoupling to AGND for pin 16(VMID) Video input coupling capacitor to pin 18(DIN) and pin 19(PIN) Capacitor between pin 32(NRESET) and DGND Pull-up resistor between pin 32(NRESET) and pin 33(DVDD3) Internal bias setting resistor between pin 13(ISET) and AGND WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 40 WM8170 Product Preview Rev 1.0 PACKAGE DIMENSIONS FT: 48 PIN TQFP (7 x 7 x 1.0 mm) DM004.C b e 25 36 37 24 E1 E 48 13 1 12 c D1 D L A A2 A1 -Cccc C SEATING PLANE Symbols A A1 A2 b c D D1 E E1 e L ccc REF: Dimensions (Millimeters) MIN NOM MAX --------1.20 0.05 ----0.15 0.95 1.00 1.05 0.17 0.22 0.27 0.09 ----0.20 9.00 BSC 7.00 BSC 9.00 BSC 7.00 BSC 0.50 BSC 0.45 0.60 0.75 o o o 0 3.5 7 Tolerances of Form and Position 0.08 JEDEC.95, MS-026 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MS-026, VARIATION = ABC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS. WOLFSON MICROELECTRONICS LTD PP Rev 1.0 March 2000 41 |
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